The need for current limitation arises in many applications, for example to provide protection for so-called “hot swap” or “hot plug” components that a user can connect to a computer system without interrupting its operation. For example, the need for inrush current limitation often arises in plug-in integrated circuit boards such as telecoms/datacoms plug-in boards, which need to be safely connected to a live backplane such as a 48 V bus. As the input capacitors that are normally provided on plug-in boards can draw a high transient current from the backplane as they charge up, charging of these capacitors needs to be current-limited in order to avoid various undesirable consequences of the high transient current, such as a dip in the backplane voltage, damage to connectors, traces or other components in the board's circuitry, or the tripping of circuit breakers in any other boards that may be connected to the backplane. Current limitation may also be required to avoid excessive inrush currents caused by input voltage transients that may occur after the board has been connected to the backplane. The structure and operation of a conventional current-limiting circuit that provides these protective functions will now be explained with reference to FIG. 1.
FIG. 1 is a schematic illustration of a plug-in board 100 having a conventional current-limiting circuit 200 that serves to connect a live backplane 300 to load circuitry that is provided, by way of example, in the form of an isolated DC/DC converter module 400 and down-stream low-voltage circuitry 500. The input capacitance of the load circuitry is represented by the input capacitor Cin that is connected between the inputs of the DC-DC converter module 400. In the present example, the current-limiting component in the current-limiting circuit 200 is a transistor Q1, which is connected in series with a current sense resistor Rs between an input terminal 210 of the current-limiting circuit 200 and an output terminal 220 of the current-limiting circuit 200, so as to provide a current path between the terminals 210 and 220 when turned ON. In the present example, the transistor Q1 is provided in the form of a power metal-oxide-semiconductor field-effect transistor (MOSFET), although another type of transistor, such as an insulated gate bipolar transistor (IGBT), may alternatively be used.
The switching and the ON-state channel resistance of transistor Q1 are controlled by the hot swap controller 230, which is arranged to monitor the transistor's drain-source current IDS (by monitoring the voltage across the current sense resistor Rs) and is operable in a current-limiting mode to limit the transistor's drain-source current (hereafter also referred to as the transistor current) when it reaches a prescribed value of IDSmax. The controller 230 limits IDS using a feedback control mechanism therein to control the gate of transistor Q1 based on the monitored current so as to keep IDS below the prescribed value of IDSmax. During current limitation, the voltage across the current-carrying channel of the transistor Q1 will vary across a range of values. For example, upon connecting the plug-in board 100 to the backplane 300, most of the backplane voltage VB will initially be dropped over the current-limiting transistor Q1, and the voltage across the transistor Q1 will then decrease as the input capacitor Cin charges.
During current limitation, the power dissipated by the transistor Q1 could exceed the maximum power Pmax which the transistor can dissipate without sustaining any damage that would degrade its performance. To protect the transistor Q1 from being damaged in this way, the controller 230 may, as in the present example, enforce a maximum power limit that cannot be exceeded during current limitation, by monitoring the drain-source voltage VDS of the transistor Q1 and controlling the transistor's gate to ensure not only that IDS does not exceed the prescribed value of IDSmax but also that the product of the monitored voltage VDS and the monitored current IDS does not exceed the maximum power Pmax.
More specifically, the controller 230 limits power dissipation by varying the target current value that is used by its feedback control mechanism as the voltage across the transistor changes, such that the power dissipated by the transistor Q1 does not exceed the maximum permitted level of Pmax. Thus, as VDS decreases during operation in the current-limiting mode, the target current value used by the controller's feedback control mechanism increases up to the prescribed value of IDSmax while the power dissipation of the transistor is being limited to Pmax at higher values of VDS. As the voltage across the transistor Q1 decreases further, the target current value is held at IDSmax to ensure that the transistor current IDS remains within safe bounds.
As an additional protective measure, the controller 230 may, as in the present example, allow current limitation to be performed by the transistor Q1 only for a set period of time. After current limitation has been performed for the set period of time (referred to herein as the transistor's “ON time”), the controller 230 turns the transistor Q1 OFF for a period of time in order to allow the transistor Q1 to cool, and this cycle of current-limited conduction followed by cooling may then be repeated until the input capacitor Cin has charged sufficiently so that IDS is no longer high enough to cause the controller 230 to operate in the current-limiting mode.
A current-limiting circuit of the type described above (hereafter referred to as “Type 1”) is provided in a number of commercially available hot swap controller boards, for example the Texas Instruments LM5067EVAL evaluation board.
A second type of current-limiting circuit (hereafter referred to as “Type 2”), which applies current limitation (but not power limitation, as in the above example) in combination with a variable transistor ON time that decreases with increasing VDS is employed in Linear Technology LTC4252 hot swap controllers, for example.
In a current-limiting circuit of a third type (“Type 3”, an example of which is provided in U.S. Pat. No. 7,408,755 B1), current limitation (but not power limitation, as in the first type of current-limiting circuit described above) with a variable transistor ON time is employed during operation in the current-limiting mode. However, in this example, the transistor ON time used during current limitation is set at a fixed value for values of VDS up to a predetermined threshold and, at higher values of VDS, decreases as VDS increases.